module fifo_syn_top(clk,rst,wr_en,rd_en,data_in,data_out);
    input clk,rst,wr_en,rd_en;
    input [7:0]data_in;
    output [7:0]data_out;
    
    wire [7:0]data_out;
    wire [7:0]data_in;
    wire [5:0]wr_addr,wr_addr_r;
    wire [5:0]rd_addr;
    
    
    fifo_syn_ram myram(.clk(clk),
                       .wr_en(wr_en),
                       .wr_addr(wr_addr),
                       .rd_en(rd_en),
                       .rd_addr(rd_addr),
                       .data_in(data_in),
                       .data_out(data_out),
                       .wr_addr_r(wr_addr_r));
   fifo_syn_wraddr_gen mywr(.clk(clk),
                            .rst(rst),
                            .wr_en(wr_en),
                            .full(full),
                            .wr_addr(wr_addr),
                            .wr_addr_r(wr_addr_r));
   fifo_syn_rdaddr_gen myrd(.clk(clk),
                            .rst(rst),
                            .empty(empty),
                            .rd_en(rd_en),
                            .rd_addr(rd_addr),
                            .wr_addr(wr_addr),.wr_addr_r(wr_addr_r));
   fifo_syn_flag myflag(.clk(clk),
                        .rst(rst),
                        .wr_en(wr_en),
                        .rd_en(rd_en),
                        .empty(empty),
                        .full(full));
  endmodule
